kicad-developers team mailing list archive

[Wayne Stambaugh <stambaughw@xxxxxxxxxxx>]

On 6/26/2012 2:18 AM, Miguel Angel Ajo Pelayo wrote:
> Hi Samuel, I also had the same problem recently (making a high power led
> controller   3x8A channels), and people complain from time to time about
> this issue,
>
> I'd be willing to see this working, but as far as I know there are
> many issues to take care of:
> cleanup code (as lorenzo said), clearance, etc. I have very little
> experience on this area, but..
>
> Jean Pierre, Wayne, what are the standard problems that he may check for?

I would make sure that the vias save to and load from file properly, the 
board clean up doesn't remove any of them, they don't cause any DRC 
issues, and the photo-plots look correct.  Other than that, I can't 
think of anything.

Wayne

> 2012/6/26 Lorenzo Marcantonio <l.marcantonio@xxxxxxxxxxxx
> <mailto:l.marcantonio@xxxxxxxxxxxx>>
>
>     On Tue, Jun 26, 2012 at 12:32:33AM +0200, Samuel Lesueur wrote:
>
>      > Anyway, I am currently designing an open source 300W DC motor
>     controller
>      > and I need a huge amount of vias to handle the current flow from
>     the top layer
>      > where my MOSFET transistors are installed to the bottom and its
>     huge GND zone.
>
>     At last a fellow power designer :D I vote yes for bottom side cooling...
>
>     The idea is very interesting since I had the same problem (I solved
>     putting the vias as pad in the fet package... as an extra it gives
>     you untented vias which have better thermal performance).
>
>     I've only a doubt... do these via 'survive' the track cleanup?
>
>     --
>     Lorenzo Marcantonio
>     Logos Srl
>
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> --
>
> Miguel Angel Ajo Pelayo
> http://www.nbee.es
> +34 636 52 25 69
> skype: ajoajoajo
>
>
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